Generally, a latch circuit is formed from a CMOS circuit. For example, as is shown in FIG. 12, a latch circuit which uses an n type MOS transistor (NMT93, NMT94) connected between a power supply line (LVDD) supplied with a VDD voltage and a power supply line (LGND) supplied with a GND voltage, and a p type MOS transistor (PMT95, PMT96) is commonly used.
FIG. 13 shows variance of a scanning pulse (φG) applied to a scanning line (LD) shown in FIG. 12, a latch control signal (φAC1) applied to a latch control line (LAC) and evoltages of each node (N91, N92, N93, N94) in accordance with time elapse.
First, the case where a voltage (data) on a signal line (LD) is a Low level (herein referred to as L level) voltage is explained. Here, before a time t1, the voltage of the node N91 is a High level (herein referred to as H level) voltage VH3, that of the node N92 is an H level voltage VDD, that of the node N93 is an L level voltage GND and that of the node N94 is an L level voltage VH4.
Next, when the latch control signal (φAC1) on the latch control line (LAC) changes from a L level voltage VL to a H level voltage VH2 at a time t2, the n type MOS transistor NMT92 is turned ON and the voltage of the node N94 becomes a voltage VL. In this way, the p type MOS transistor PMT95 and the n type MOS transistor NMT94 are turned ON, the p type MOS transistor PMT96 and the n type MOS transistor NMT93 are turned OFF, the voltage of the node N92 (output terminal (OUT2)) becomes a L level voltage GND, and that of the node N93 (output terminal (OUT1)) becomes a H level voltage VDD.
Next, the case where a voltage (data) on a signal line (LD) is H level voltage VDH is explained. Here, before a time t3, the voltage of the node N91 is an L level voltage VL, that of the node N92 is an L level voltage GND, that of the node N93 is an H level voltage VDD, and that of the node N94 is an L level voltage VL.
As is shown in FIG. 13, when the scanning pulse (φG) on the scanning line (LG) changes from a L level voltage VL to a H level voltage VH1 at a time t3, the n type MOS transistor NMT91 is turned ON, and a voltage (data: here a voltage VDH) on the signal line (LD) is input to a storage capacitance (CD). In this way, the voltage of the node N91 becomes a voltage VH3. Next, when the latch control signal (φAC1) on the latch control line (LAC) changed from a L level voltage VL to a H level voltage VH2 at a time t4, the n type MOS transistor (NMT92) is turned ON and the voltage of the node N94 becomes a voltage VH4. In this way, the n type MOS transistor (NMT93) and the p type MOS transistor (NMT96) are turned ON, the p type MOS transistor (PMT95) and the n type MOS transistor (NMT94) are turned OFF, the voltage of the node (N92) (output terminal (OUT2)) becomes a H level voltage VDD, and the voltage of the node (N93) (output terminal (OUT1)) becomes a L level voltage GND.
As is shown in FIG. 14, a pixel circuit of a display (referred to below as a movable shutter type display) which electrically controls the position of a movable shutter (s) to display an image in accordance with output signals from two output terminals (OUT1, OUT2) of the latch circuit is a specific usage example of the latch circuit shown in FIG. 12. Furthermore, a movable shutter type display is disclosed for example in Patent Document 1 (Japanese Laid Open Patent 2008-197668).
In the pixel circuit of the movable shutter type display shown in FIG. 14, the movable shutter (s) moves at a high speed in the direction of an electric field. As a result, in case the voltage of the node N92 is GND and that of the node N93 is VDD, the movable shutter (s) moves to the node N93. In the case the voltage of the node N92 is VDD and that of the node N93 is GND, the movable shutter (s) moves at a high speed to the node N92. In addition, for example, in the case where the movable shutter moves to the node N92, light from a backlight unit passes through it and a pixel becomes a light emitting state, and in the case where the movable shutter moves to the node N93, light from a backlight unit does not pass through it and a pixel becomes a light non-emitting state. In this way, it is possible to display image as if it were a liquid crystal display panel or a plasma display panel. Furthermore, in FIG. 14, LSS is a movable shutter control line supplied with a shutter control signal (φS).
FIG. 15 is a block diagram which shows an approximate structure of a movable shutter type display. In the movable shutter type display shown in FIG. 15, a plurality of pixel circuits shown in FIG. 14 each corresponding to 1 pixel (PX) are arranged in 2 dimensions. Here, the scanning line (LG) is arranged on each row of which signal is input to a vertical drive circuit (XDR). In addition, a signal line (LD) is arranged on each column of which signal is input to a horizontal drive circuit (YDR). Power supply lines (LVDD, LGND), the latch control line (LAC) and the movable shutter control line (LSS) are commonly arranged on each pixel to input signals to the horizontal drive circuit (YDR). In the movable shutter type display shown in FIG. 15, data is programmed to each pixel on each row within a programming time period (TA in FIG. 13), and within a movable shutter state setting time period (TB in FIG. 13), the movable shutter (s) is made to move to the node N92 or the node N93 and an image is displayed in a display time period (TC in FIG. 13).
As is shown in FIG. 12, a circuit configuration in which a latch circuit is configured of a CMOS circuit is currently widely used and has proven actual results. However, for example, when attempting to apply a latch circuit configured of the CMOS circuit shown in FIG. 12 for high voltage use (for example, for use with a voltage where a potential difference between a voltage VDD and a voltage GND is 20V or more) using a MOS transistor in which polycrystalline silicon (polysilicon) is used for a semiconductor layer, it is assumed that the characteristics of a thin film transistor deteriorate due to a drain avalanche effect and doubts concerning reliability arise.
The present invention was performed in order to solve these conventional technological problems. The aim of the present invention is to provide a latch circuit which is capable of controlling a drain avalanche effect and improving reliability, and a display device which uses this latch circuit. The aim of the present invention and other aims and new characteristics are made clear with reference to the descriptions of the present specification and attached drawings.